1. Field of the Invention
The present invention relates to a semiconductor memory device configured to read and write data stored in memory cells, and particularly relates to a semiconductor memory device employing an open bit line structure such as a DRAM (Dynamic Random Access Memory).
2. Description of Related Art
Conventionally, an open bit line structure and a folded bit line structure have been known as an array structure employed in a memory cell array divided into a plurality of memory mats in a DRAM. In the DRAM of the open bit line structure, a pair of bit lines connected to a sense amplifier is extended to memory mats different from each other. Meanwhile, in the DRAM of the folded bit line structure, a pair of bit lines connected to a sense amplifier is extended to the same memory mat. Generally, arrangement of memory cells of the folded bit line structure is restricted so that a cell size of each memory cell is supposed to be limited to 8F2 (F is a minimum processing dimension). On the contrary, memory cells of the open bit line structure can be arranged at all intersections of word lines and bit lines so that each memory cell can be formed with a cell size of 6F2. Thus, it is appropriate to employ the open bit line structure in order to improve integration of the DRAM. The DRAM of the open bit line structure is configured with a structure in which a plurality of normal memory mats are aligned in a bit line extending direction and end memory mats are arranged at both ends thereof. Each end memory mat has the same size as each normal memory mat, and due to its structure there are arranged dummy cells in a half area of the end memory mat. Thus, memory capacity of the end memory mat is half that of the normal memory mat and the end memory mat has the same size as the normal memory mat, thereby correspondingly decreasing area efficiency of the DRAM. Meanwhile, a technique to improve the area efficiency in the DRAM of the open bit line structure using a special configuration of end memory mats has been proposed (for example, refer to Patent Reference 1).
Patent Reference 1: Japanese Patent Application Laid-open No. 2007-5502
In the technique disclosed in the Patent Reference 1, the normal memory mats are formed with memory cells of 6F2 having the open bit line structure, and the end memory mats are formed with memory cells of 8F2 having the folded bit line structure, thereby improving the area efficiency without using dummy cells. However, when employing the technique disclosed in the Patent Reference 1, memory cells whose cell size is 6F2 and memory cells whose cell size is 8F2 are mixed, and there arises a problem that process technique of the DRAM becomes complex because of a difference of memory cell structures. Further, in consideration of the difference between memory cell structures of the end memory mat and the normal memory mat, the area of the end memory mats is merely about two-thirds of the area of the normal memory mats even if the dummy cells are not required, which is a problem of difficulty in remarkably improving the area efficiency.